AMD triples Zen 3 CPU cache using 3D stacking technology

Yesterday at Computex 2021, AMD CEO Lisa Su confirmed off the company’s following big performance play—3D stacked chiplets, enabling the enterprise to triple the quantity of L3 cache on its flagship Zen 3 CPUs.

The technological innovation is just what it seems like—a layer of SRAM cache sitting down atop the Complicated Core Die (CCD) of the CPU itself. Existing Zen 3 architecture integrates 32MiB of L3 cache for each 8-core chiplet—making 64MiB overall for a 12- or 16-core chiplet like the Ryzen 9 5900X or 5950X. The new know-how provides an supplemental 64MiB L3 cache on major of each and every chiplet’s CCD, bonded with by way of-silicon vias (TSVs).

The additional 64MiB L3 cache layer does not extend the width of the CCD, ensuing in a require for structural silicon to stability pressure from the CPU cooling system. Compute and cache dies are both thinned in the new design, letting it to share substrate and heat spreader technological know-how with present Ryzen 5000 processors.

Tripling the L3 cache on Ryzen 5000 enables functionality gains under some workloads—particularly archive compression/decompression and gaming—similar to all those found with complete new CPU generations. AMD shown functionality uplift via a Gears of War 5 demo. Paired with an unspecified GPU and with clock pace fastened at 4 GHz, a current-design 5900X system realized 184 fps—while the triple-cached prototype managed 206 fps, a get of about 12 per cent.

AMD claims an ordinary of 15 p.c improved gaming efficiency with the new technological innovation, ranging from a small of 4 percent for League of Legends to a significant of 25 percent for Monster Hunter: Planet. This performance enhancement demands neither smaller sized system node nor elevated clock speed—which is especially attention-grabbing, in an period where clock speeds have mostly strike a wall, and a physics-decided conclusion to process-node shrink seems to be on the horizon as perfectly.

Anandtech’s Ian Cutress notes that AMD’s new 3D chiplet stacking procedure is obviously TSMC’s SoIC Chip-on-Wafer technological know-how in motion. Whilst AMD is—at minimum so far—limiting by itself to two levels, TSMC has shown a comprehensive 12 levels in motion. The challenge listed here is thermal—adding RAM is a near-great use of the technology, given that the extra silicon isn’t going to deliver considerably in the way of more warmth. Stacking CPU on CPU would be considerably a lot more problematic.

AMD states that the redesigned 5900X will enter creation afterwards this year—well just before Zen 4’s scheduled start in 2022. For now, AMD is focusing on the new technological innovation for “large-stop Ryzen” CPUs only—no mention was produced of Epyc, and the added silicon essential for the additional cache can make it a possible nonstarter for spending budget processors, given current products shortages.

Listing impression by AMD

Leave a Reply